| 摘要 |
PURPOSE: To process minimum or maximum calculation of a pair of operands with only one instruction cycle by performing a conditional test of a minimum or maximum operand and load to an accumulator register in parallel with a subtraction operation between operands by an arithmetic and logic unit. CONSTITUTION: An arithmetic and logic unit ALU accepts respective 1st and 2nd operands to 1st and 2nd inputs, executes subtraction and outputs information bits on the operation in its execution mode. A digital processor further has a conditional circuit COND to decide maximum and minimum operands. The conditional circuit COND receives the bit of digit position value (n-1) which is a code bit of operation result, a 1st bit for a carry into the code bit of the bit of digit position (n-2) and a 2nd bit which exceeds the code bit to carry, and outputs a conditional instruction to transfer the operand which is decided in this way to an accumulator register A. |
