发明名称 |
Shallow trench isolation process for high aspect ratio trenches |
摘要 |
Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.
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申请公布号 |
US5492858(A) |
申请公布日期 |
1996.02.20 |
申请号 |
US19940230180 |
申请日期 |
1994.04.20 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
BOSE, AMITAVA;GARVER, MARION M.;NASR, ANDRE I.;COOPERMAN, STEVEN S. |
分类号 |
H01L21/762;(IPC1-7):H01L21/76 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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