| 摘要 |
A system and method are provided for disabling the edge transition detection circuit during the flash clear cycle, thereby preventing the generation of an edge transition detection pulse. In a preferred embodiment of the invention, the edge transition detection circuit is connected to the flash clear complement circuitry through a logic gate. During the flash clear cycle, flash clear true, FCT, is pulled high, flash clear complement, FCc, is pulled low and inverted to drive a portion of the ETD circuitry high, thereby preventing generation of an ETD pulse during the flash clear cycle.
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