| 摘要 |
PURPOSE:To provide a format conversion circuit which can reduce its scale despite a large quantity of input data. CONSTITUTION:This circuit performs the conversion of a format with the serial data including (n) rows of (m) bits arrayed in parallel to each other defined as one group and contains a generation means LP which generates a load pulse signal P2 every (m) bits based on a frame pulse signal P1 showing the head of the serial data and a conversion means 100 which includes FF (flip-flops) of staves of (m+1) bits connected in series with intervention of the 2:1 SEL (selectors). Then (n) rows of such series connection are arrayed in parallel to each other with a 1st input terminal of each SEL connected to the output terminal of the FF of the precedent stage and this FF output terminal is connected to the input terminal of the FF of the next stage respectively. A 2nd input terminal of the SEL which is selected when the signal P2 is supplied is connected to the output terminal of each FF so that the data are held by the FF of the output terminal side of the SEL in an array subjected to a conversion format when the signal P2 is supplied. |
