| 摘要 |
The circuit is for designating channels to be processed by a DSP and for synchronizing the channels. The circuit includes a counter(7) for synchronizing clock signals to a frame synchronous signal and for dividing the clock signal, a decoder(8) for generating a channel designating signal by decoding an output signal of the counter(7), a multiplexor(9) for selecting output signal of the decoder(8)an OR gate(10) for providing channel designating signal to DSPs(1-4), D-flipflops(11-14) for providing channel synchronous signal to the OR gate(10), and a delay unit(40) for delaying a frame synchronous signal and sending the delayed signal to the D-flipflop(11-14).
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