| 摘要 |
The oscillating frequency of an oscillator in a DRAM is decreased at standby mode by using the inverter so that power consumption at the standby mode is decreased. The inverter includes a transmission gate(10) for outputting a signal by control signals(VCON1, VCON2), a 11th inverter(11) for receiving the output signal of the gate and for outputting the signal by a low address signal(RASF11), a 12th inverter(11) for receiving the output signal of the 11th inverter and for outputting the signal by a low address signal(RASF12), a 13th inverter(11) for receiving the output signal of the 12th inverter and for outputting the signal by a low address signal(RASF13), a 14th inverter(11) for receiving the output signal of the 13th inverter and for outputting the signal by a low address signal(RASF14), a 15th inverter(11) for receiving the output signal of the 14th inverter and for outputting the signal by a low address signal(RASF15).
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