发明名称 PARALLEL MULTIPLICATION LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the size of an increment device by generating the set of input signal from the set of signals received by the increment circuit by the change of the signals of the set of received signals according to the action of a control signal received by a logic circuit. SOLUTION: A calculating circuit 4 is provided with an increment circuit 10, and the increment circuit 10 receives as the input an intermediate set P"o and signals TCX, TCY, I, RND. This increment circuit 10 outputs a set P(3) 0 of signals as one output. The purpose of this increment device 10 is to estimate valid increment normally generated from the formatting of an output set for rounding this increment when the result of rounding off is desired. Then, the set of input signals are generated from the set of signals received by the increment circuit 10 by the change of the signals of the set of received signals according to the action of a control signal received by a logic circuit.
申请公布号 JPH0844540(A) 申请公布日期 1996.02.16
申请号 JP19950202804 申请日期 1995.07.17
申请人 SGS THOMSON MICROELECTRON SA 发明人 FUIRITSUPU PARAN
分类号 G06F7/53;G06F7/507;G06F7/52;G06F7/533 主分类号 G06F7/53
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