| 摘要 |
<p>PURPOSE:To realize excellent performance to price and to increase the read speed by simultaneously latching data by latch circuits in all blocks. CONSTITUTION:A ROM where instructions are stored is divided into ROMs 100 to 103, and in each block, data corresponding to addresses 4N, 4N+1,...4N+3 (N is not negative and an integer) are stored in ROMs 100 to 103 respectively. An address decoder 7 expands the address subjected to required translation in an address translation circuit 5 to actually access the memory cells of ROMs 100 and 101. Meanwhile, output data of moss 100 to 103 are latched by data latches 200 to 203. Data buffers 300 and 303 are opened/closed by gate signals 400 to 403 outputted from a data selector 11. Consequently, data in addresses 4N, 4N+1,...4N+3 are certainly read out at each time of one latch operation when the read start address is 4N or 4N+1.</p> |
