| 摘要 |
<p>PURPOSE: To support an integrated processor and a high performance peripheral equipment with lower performance and lower costs, without sharply increasing the number of pins in the integrated processor. CONSTITUTION: A computer system 200 includes an integrated processor 210 connects to a power managing device 202 and at least one peripheral equipment, including a bus interface device which interfaces with a multiplexed address/data line and a high performance peripheral distribution bus. The peripheral distribution bus operates data transfer between the inside bus of an integrated processor and a PCI(peripheral component interconnect) peripheral equipment. The integrated processor is provided with a sub-bus controller which generates several side band control signals, enabling the outside generation of a secondary bus with lower performance such as an ISA bus, and it is not necessary to provide the complete number of outside pins for the secondary bus on the integrated processor. The generation of the secondary bus is done by an outside data buffer and outside address latch, controlled by a side band control signal.</p> |
