发明名称 |
Memory with stress circuitry for detecting defects |
摘要 |
A memory circuit is disclosed with stress circuitry for detecting data retention defects in the memory cells. The memory circuit comprises a memory cell array coupled to bit lines, an access circuit coupled to access the memory cells, and a discharge circuit coupled to stress the memory cells. |
申请公布号 |
AU2865195(A) |
申请公布日期 |
1996.02.16 |
申请号 |
AU19950028651 |
申请日期 |
1995.06.16 |
申请人 |
INTEL CORPORATION |
发明人 |
EITAN ROSEN;YAKOV MILSTAIN |
分类号 |
G01R31/28;G11C11/413;G11C29/06;G11C29/50 |
主分类号 |
G01R31/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|