| 摘要 |
<p>PURPOSE:To facilitate processing of bit line selection transistor by forming bit line selection transistors almost in the same shpae as a selection transistor and then arranging the selection transistor to the position where the selection transistor is moved in parallel in the bit line direction. CONSTITUTION:The bit line selection transistors Qn4, 5 are formed adjacent to NAND cell unit within a memory cell array formed on a p-type well. The source/drain thereof is the n-type diffused layer 4 which forms the source/drain of the selection transistor and the gate electrode thereof is formed by a wiring layer 2 in the same gate length. The bit line selection transistors Qn4, 5 can be formed almost in the same shape by forming them simultaneously with the selection transistor. Processing of the bit line selection transistors can be done easily while keeping the regular shape of the memory cell array by forming the bit line selection transistors Qn4, 5 with the selection transistors in the memory cell.</p> |
