发明名称 CLOCK GENERATING CIRUCIT
摘要 PURPOSE:To realize the simple configuration with low power consumption operated stably and to eliminate the need for the adjustment. CONSTITUTION:The clock generating circuit is provided with a communication equipment receiving same transmission signals from each transmission line of each system including a redundant system and selecting one of the transmission signals and processing the selected signal and generates a clock signal in the communication equipment based on any of the transmission signals. A frequency division section 52-0 (52-1) of each system frequency-divides a clock signal extracted by a clock extract section 22-0(22-1) of each system to generate a system reference signal to be given to a phase locked loop circuit 41. A selection section 53 selects a system reference signal based on a switching signal from switching signal generating means 51-0, 51-1, 54 among the reference signals of each system and gives the selected reference signal to the phase locked loop circuit. Then the reference signal selected by the selection section is fed back to the frequency division section of all the systems to initialize the frequency divider sections of all the systems.
申请公布号 JPH0846601(A) 申请公布日期 1996.02.16
申请号 JP19940176422 申请日期 1994.07.28
申请人 OKI ELECTRIC IND CO LTD;NIPPON TELEGR & TELEPH CORP <NTT> 发明人 TANAKA TAKAYUKI;HASHIBA MASAHARU
分类号 H03L7/08;G06F1/04;H04L1/22;H04L7/00;H04L7/033 主分类号 H03L7/08
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