发明名称 CONTROLLING SYSTEM FOR FAULT RESISTANT COMPUTER
摘要 PURPOSE:To suppress the propagation of a fault at a minimum even when the fault is generated by comparing the input data and output data of plural microprocessors (MPU). CONSTITUTION:A basic processor 20 is composed of three MPU 201-203, input/ output data check circuit 204 for the MPU 201 to 203, fault propagation preventing circuit 205, timers 207 to 208 connected to the input/output data check circuit 204 and an internal bus, and encoder 206 for converting an interruption request signal 20531 from the fault propagation preventing circuit 205 and interruption request signals from the timers 207 and 208 to interrupting signals to the MPU 201 to 203, or the like. Thus, the input data are compared in addition to the conventional comparison of output data concerning the MPU 201 to 203 to be synchronously operated. When the unequal comparison occurs the comparison, in the case of input data, the part of the fault is specified by the self-diagnostic processing of MPU 201 to 203 or in the case of output data, it is specified by majority processing and disconnecting processing is performed.
申请公布号 JPH0844682(A) 申请公布日期 1996.02.16
申请号 JP19940176423 申请日期 1994.07.28
申请人 HITACHI LTD 发明人 HIUGA KAZUHIRO;FUKUMARU HIROAKI;MIYAZAKI YOSHIHIRO;TANJI MASAYUKI;NAKAMURA AKIHISA;YAMAGUCHI SHINICHIRO
分类号 G06F11/18;G06F11/00;G06F15/16;G06F15/177 主分类号 G06F11/18
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