| 摘要 |
PURPOSE: To provide a simple manufacturing method of a heterojunction bipolar transistor with decreased parasitic capacitance in the base-collector junction. CONSTITUTION: Substrates 24 and 28, a collector layer 22 on the substrate, a base layer 12 on the collector layer 22, a base contact 16, an emitter layer 10, and an emitter contact 14 are provided. Filling a dielectric material 30 in the region where the base 12 and a part of the collector layer 22 extended outside from the emitter layer 10 is removed, and bonding the base contact 16 extended to the base 12 on the dielectric material 30, make it possible to minimize the parasitic capacitance related to the base-collector junction.
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