| 摘要 |
PURPOSE:To stop a PLL circuit completely without generating a DC path by controlling a voltage controlled oscillator so as not to be oscillated in response to a reset signal and making a phase difference of two clock signals zero. CONSTITUTION:The operation of a PLL circuit 1000 when a reset signal 104 is at a high level is similar to that of a conventional method. When the signal 104 is at a low level, signals 105, 106 outputted from an input interrupt control circuit 14 go to a low level. As a result, since a phase difference between the signals 106, 106 is zero, an output signal 101 from a phase comparator 11 is zero. A loop filter 12 trys keeps a voltage of the signal 102. However, since the voltage of the signal 102 is pulled down to 0V by a voltage fixing control circuit 15, the voltage of the signal 102 is st to 0V. As a result, since a voltage controlled oscillator 13 is not oscillated, the output of the oscillator 13 goes to a low level. |
