发明名称 TIMER TRAPPING CIRCUIT AND INFORMATION PROCESSOR
摘要 <p>PURPOSE:To suppress the expansion of a hardware circuit without increasing the load on a CPU and reducing the efficiency of the whole device by recording plural timer values at a time interval counted by a timer counter by the use of a memory element. CONSTITUTION:The address range of a 1st storage means 4 is counted by a counting means 5 based upon a prescribed input clock signal 101 and timer values stored in the means 4 are read out and addressed. An interruption detecting circuit 10 monitors the output of the means 4 and a timer value set up by a processing means 2 which is an output from a 2nd storage means, detects the timer value set up by the means 2 by the identity of both data, and at the time of detecting the timer value, outputs an interruption request to the means 2. Since a memory element or the like is used as a storage means for storing timer values, plural timer values can be recorded only by one storage means even in the case of using many timer values in order to measure a specific time interval, so that the size of the hardware circuit can be reduced.</p>
申请公布号 JPH0844456(A) 申请公布日期 1996.02.16
申请号 JP19940175813 申请日期 1994.07.27
申请人 MITSUBISHI ELECTRIC CORP 发明人 KANO TOMOO
分类号 G06F1/14;H03K21/00;(IPC1-7):G06F1/14 主分类号 G06F1/14
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