| 摘要 |
<p>PURPOSE:To dispense with a wasteful time required for changing over word lines at the time of consecutive readouts of data for plural pages by dividing bit line transfer gates and sense-amplifier and latch circuits into two plural groups and independently driving different groups while executing a timing control, CONSTITUTION:Bit line transfer gates 3 and sense-amplifier and latch circuits 2 of a memory cell array 1 are divided into two groups of bit line transfer gates and sense-amplifier and latch circuits 3A and 2A, 3B and 2B. Then, respective groups are controlled with different timings and at the time the half of a page is read out from one of circuits 2A, 2B, the other latches the other half of the page. Thus, since random readout operations of word lines are unnecessitated at the time of consecutive readouts of plural pages, a high speed consecutive page readout is performed without increasing a chip area and without the wasteful time required for changing over word lines.</p> |
