| 摘要 |
A circuit for use in a multi-valued logic non-volatile storage system, where the circuit optimises the storage capacity of each of the cells in the storage system. The optimising process is performed by determining the linear range of the storage cells, applying an offset derived from calibrated reference sites containing maximum and minimum useful values of the gate voltage to ensure that operation is only within that linear range, followed or preceded by applying a scaling voltage to expand or attenuate the linear range. |
