| 摘要 |
PURPOSE:To prevent occurrence of the program runaway by detecting a 2nd parity error which is generated during processing of a 1st parity error. CONSTITUTION:A parity error checker 2 detects the 1st parity error and transmits the detecting signals to a flip-flop 3 and a gate 51. The flip-flop 3 holds the received detecting signal and transmits an NMI interruption signal to an MPU 1 to start a parity error processing program PEP. The parity error if produced again during the parity error processing is detected by the checker 2. Then the checker 2 sends a detecting signal to the gate 51. The gate 51 receives the detecting signal as well as the signal which is having the parity processing. Thus the signal 'H' is outputted to a flip-flop 52. The flip-flop 52 holds the signal 'H' and delivers a halt signal HALT to the MPU 2. Thus the working of the MPU 1 is stopped and the program runaway is prevented. |
