| 摘要 |
Quality requirements on a counter may set a limit to the highest frequency that can be applied to the counter. This will also limit the resolution. According to the invention there is provided a counter comprising a generator for generating, in response to a first clock frequency, M second clock signals phase shifted with respect to each other and of a second frequency lower than the first frequency, and M secondary counters, each one responsive to a respective one of the M second clock signals for generating a secondary counter signal. The second frequency is adapted to work well in the technology available for realizing the secondary counters, with consideration taken to quality requirements. Furthermore, the counter comprises a summing circuit responsive to the secondary counter signals for generating the resulting counter signal by adding the secondary counter signals such that the counter signal has the same number of bits and the same significance as the secondary counter signals. |
