发明名称 |
Method and apparatus for synthesizing datapaths for integrated circuit design and fabrication |
摘要 |
A method for fabricating an integrated circuit includes the steps of: (a) developing a set of circuit specifications for an integrated circuit; (b) encoding the set of circuit specifications in a hardware description language (HDL); (c) synthesizing a netlist including a sequential datapath with a datapath synthesizer from the HDL; and (d) fabricating an integrated circuit as specified by the netlist. A method for datapath synthesis includes the steps of: (a) providing a datapath library including sequential components and combinational components; (b) developing a set of circuit specifications for an integrated circuit; (c) encoding the set of circuit specifications in a HDL; (d) developing a number of IC expression trees derived from the HDL; (e) matching the IC expression trees with library expression trees derived from the datapath library to provide a map of matches; and (f) synthesizing according to the map to create a datapath netlist including both sequential datapaths and combinational datapaths. A datapath synthesizer includes a digital processor, memory coupled to the digital processor, and a datapath library stored in the memory. An input device is used to input a HDL description of circuit specifications into memory, and an IC expression generator develops a number of IC expression trees from the HDL. A matcher compares the plurality of IC expression trees with library expression trees derived from the datapath library to provide a map of matches, and a synthesizer provides a netlist including both sequential datapaths and combinational datapaths according to the map.
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申请公布号 |
US5491640(A) |
申请公布日期 |
1996.02.13 |
申请号 |
US19940272205 |
申请日期 |
1994.07.08 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
SHARMA, BALMUKUND K.;MAHMOOD, MOSSADDEQ |
分类号 |
G06F17/50;(IPC1-7):G06F15/60 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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