Apparatus for reducing current consumption in a CMOS inverter circuit

摘要

A method and system for reducing pass-through current. The amount of simultaneous current flow through p-channel and n-channel devices of a CMOS inverter is reduced. This results in an increase in the power efficiency of CMOS oscillators, inverters, gates and other CMOS circuits. Another benefit of this invention is the increase of the output signal magnitude. This increase in the output signal with the lower power consumption yields a significantly higher efficiency of the CMOS circuit such as an oscillator.