| 摘要 |
A data latch circuit comprises a non-volatile memory cell (11) having its threshold voltage changed in accordance with data to be stored therein, and a latch circuit (60). The cell (11) has a transistor (T3) for writing data and a transistor (T4) for reading data. The writing and reading transistors (T3, T4) has a common floating gate. The reading transistor (T4) has a threshold voltage lower than the writing transistor (T3). During normal operation, a ground potential (Vss) is applied to the control gate of the reading transistor (T4). The latch circuit (60) latches data in accordance with whether the non-volatile memory cell (11) is in the on-state or off-state. <IMAGE> |
