发明名称 |
DIGITAL PHASE LOCKED LOOP |
摘要 |
A digital phase locked loop is for recovering a stable clock signal from at least one input signal subject to jitter is disclosed. The loop comprises a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in said output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator, and a tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled oscillator. The tapped delay line produces an output signal from a tap determined by the control signal. A digital phase comparator receives at least one input signal from the input circuit and the output signal from the tapped delay line to generate a digital input signal controlling the digital controlled oscillator. |
申请公布号 |
WO9603808(A2) |
申请公布日期 |
1996.02.08 |
申请号 |
WO1995CA00432 |
申请日期 |
1995.07.20 |
申请人 |
MITEL CORPORATION |
发明人 |
WIECZORKIEWICZ, JERZY;SHETTY, KRISHNA;KENNEY, TERRY;VAN DER VALK, ROBERT, L.;SPIJKER, MENNO, T. |
分类号 |
H03L7/06;H03L7/081 |
主分类号 |
H03L7/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|