| 摘要 |
<p>PURPOSE:To prevent an output of an apparently normal data in a transmission signal by supervising a period of a reception signal frame timing pulse, and fixing a transmission signal to '0' when there is any fault in the period. CONSTITUTION:A reception signal frame timing pulse RDF and an overflow pulse of a write address counter circuit 2 are inputted to an exclusive OR circuit 4, its output pulse is supervised by a D flip-flop circuit 5 to decide whether or not a period of the reception signal frame timing pulse RDF is normal. The output signal of the D flip-flop circuit 5 and a readout signal from the memory circuit 1 are ANDed by an AND circuit 6 and when the period of the reception frame timing pulse RDF is abnormal, the transmission signal TD is fixed to 0. Thus, it is prevented that an apparently normal data is outputted as the transmission signal regardless of the production of a fault in the reception signal.</p> |
