| 摘要 |
<p>PURPOSE:To shorten the delay time of data with respect to the internal clock in a reference device and to secure a sufficient hold time for a peripheral device in the reference device by supplying the clock to be supplied to the peripheral device to an internal circuit of the reference device through a clock input circuit to. CONSTITUTION:In the signal processing system where plural peripheral devices are connected to a reference device 2 incorporating a reference clock generation circuit, a clock output CKOUT of a clock output circuit 14 sent to a clock output terminal 15 is supplied to an internal circuit 18 through a clock input circuit 21 as an internal clock CLK. That is, the clock from the reference clock generation circuit is sent to the clock output terminal 15 through the clock output circuit 14 and is supplied to peripheral devices, and the clock input circuit 21 is connected to the clock output circuit 14, and the clock CLK outputted from this circuit is supplied to the internal circuit 18 of the reference device 2. Thus, data is transferred between plural devices based on the high speed clock.</p> |
