PHASE-LOCKED CIRCUIT

摘要

PURPOSE:To generate a stable reference clock by measuring the time difference between the rise of a high speed clock and that of a horizontal synchronizing signal at the stage of delay elements and outputting the clock which has passed through delay elements whose number of stages corresponds to it. CONSTITUTION:An inputted reference clock 16 successively passes delay elements 11 to generate the clock delayed by a certain time. The logical level of the reference clock 16 at the instant of the rise of a trigger signal 17 is stored in a storage element 12. An edge detection element 13 makes the output active when output patterns of two adjacent storage elements 12 are in the high level in the preceding stage and in the low level in the succeeding stage. A 3-state buffer 14 leads the output or the delay element 11 to an output circuit 15 by the output of the edge detection element 13. The output circuit 15 operates wired-OR among outputs of plural 3-state buffers 14 and leads the result to an output 18. Thus, the output 18 is obtained which rises approximately synchronously with the trigger signal 17 and has the same frequency as the reference clock 16.