| 摘要 |
An output buffer circuit with edge-rate control capable of maintaining both rising and falling edge-rates within narrow specifications in the face of wide variations in load impedance. In particular, the output buffer of the present invention is intended for coupling to a common bus whereby it may be presented with very low resistive impedance loads and varying capacitive loads. The control schemes for both the pull-up and the pull-down parts of the circuit of the present invention utilize in part fixed currents charging a selected capacitance in order to achieve a metering of the charging or discharging current at the buffer's output. For the pull-down part of the circuit a dual MOS/Bipolar pull-down scheme is used, with the MOS transistors sequentially turning on in a gradual fashion so as to smooth the onset of current sinking. Subsequently, after a measured delay, a bipolar pull-down transistor is turned on. There is also a contingent bipolar pull-down transistor to aid in switching the buffer output from logic-high to logic-low if the MOS transistors and first bipolar transistor acting together are not sufficient. Later, as current-sinking is being turned off, there is again a sequential deactivation of the pull-down transistors so as to round the turn-off curve. The dual MOS/bipolar pull-down scheme provides a degree of temperature compensation of the pulldown current and a lower output capacitance than when one type of transister is used.
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