发明名称 SEQUENTIAL DIGITAL ADAPTIVE EQUALIZER
摘要 PURPOSE:To reduce the scale of memory and the like capacity without deteriorating the equalization characteristic by conducting training based on a training signal in the middle part of a burst signal and applying equalizing processing to data parts before and after tne training signal separately. CONSTITUTION:A burst signal formed by inserting a training signal between data parts is received and stored in a buffer memory 1. The training signal in the burst signal is read and a propagation path impulse response calculation section 2 calculates an impulse response of the propagation path by reading the training signal in the burst signal and using a know training signal. When the processing as to the training signal is finished, the data part before or after the training signal is sequentially read from the buffer memory 1. Then a replica signal based on the impulse response and an equalizing output signal is generated from a replica generating section 3 and adder 5 is used to eliminate a delay wave component and an the result is inputted to a sequential equalization section 4. The sequential equalization section 4 uses the sequential decoding algorithm such as fano algorithm or stack algorithm to conduct equalization processing and an equalization output signal is obtained.
申请公布号 JPH0837479(A) 申请公布日期 1996.02.06
申请号 JP19940170738 申请日期 1994.07.22
申请人 FUJITSU LTD 发明人 HAMADA HAJIME;UCHIJIMA MAKOTO;YAMASHITA ATSUSHI;NAKAMURA MICHIHARU
分类号 H03H21/00;H03H15/00;H03H17/00;H03M13/23;H04B3/10;H04L27/01 主分类号 H03H21/00
代理机构 代理人
主权项
地址