| 摘要 |
PURPOSE:To normally store data without being affected by a phase difference by receiving each clock signal from the side of a duplex device and changing a switching control signal in synchronism with a clock at the switching destination of a system. CONSTITUTION:The output of a switching control signal 3 is commonly inputted to F/F 151 and 152, the F/F 151 normalizes that output with the clock received from a system '0' and the F/F 152 normalizes it with the clock received from a system '1'. Therefore, their Q outputs can be provided as waveforms 7 and 7'. Those waveforms 7 and 7' are respectively applied as one input signal of AND gates 154 and 155 and the other input signals are respectively the output signal of an inverter 153 and the switching control signal 3. Therefore, when the switching control signal 3 is at an L level, the output of the AND gate 154 is validized and when it is at an H level, the output of the AND gate 155 is validized so that output signals 8 and 8' can be obtained. These signals 8 and 8' are applied to an OR gate 156 and a corrected switching control signal 3' is obtained. |
