| 摘要 |
PURPOSE:To reduce a memory capacity of an interleave circuit of the error correction coder. CONSTITUTION:An FEC coder 1 codes an input digital information signal. An interleave circuit 3 interleaves an output of the coder 1. A signal arrangement distributer 5 projects an output of the interleave circuit 3 respectively onto I and Q axes to provide an output of modulation symbols Ie, Qe. The memory capacity of the interleave circuit 3 is enough to be an output of the coder 1, that is, bit number being a product between number of bits required to express digital information of one modulation symbol and a modulation symbol number. |
