| 摘要 |
PURPOSE:To attain stable clock recovery independently of a reception state or a content of received data by replacing a clock signal extracted from a burst signal with a reference clock signal. CONSTITUTION:A clock extract circuit 52 extracts a clock signal and the signal is outputted as a clock output 5 via a time limiter circuit 53 and a 2:1 selection circuit 4 and given to a timing generating circuit 6. A reference clock signal outputted from a 1/N frequency divider circuit 2 and the clock output 5 are synchronized based on a load pulse generated by the circuit 6. Thus, after the phases of the two clock signals are matched with each other, an external selection signal 3 is given to the circuit 4 to allow the circuit 4 to replace the clock signal extracted from the burst signal with the reference clock signal outputted from the circuit 2 as the clock output 5. Thus, stable clock recovery is executed at all times. |
