CACHE CONTROL SYSTEM FOR DISTRIBUTED MEMORY TYPE PARALLEL COMPUTER

摘要

PURPOSE:To provide a system for speeding up operation by extending a cache area by using a part of a main memory as a cache area and reducing the probability of transferring data from a remote processing element(PE) in a distributed shared memory system for operating main memories distributed in respective PEs as if one large memory space exists in the whole system of a distributed memory type parallel computer. CONSTITUTION:A processor 1 transfers an address to an address detecting means 4 in a cache area accessing part 3 through an address bus 2. When a tag is hit in the detecting part 4, an address generated by an address conversion part 10 is transferred to a main memory control device 6. A cache area 9 is included in a part of a main memory 8. The area 9 is constituted of dividing a part of the area of the memory 8 and both the main memory 8 and cache area 9 are accessed by the device 6.