| 摘要 |
PURPOSE:To make the size small, the weight of the circuit light and to reduce the cost by arranging a clock inhibit circuit to a post-stage of an S/P conversion circuit so as to integrate the clock inhibit circuit into an IC for a special application operated at a low speed. CONSTITUTION:A phase selection circuit 12 detects the coincidence of bit phases between n-series of comparison pattern signals g1 outputted from a comparison pattern generating circuit 7 and n-series of input data signals b1 outputted from an S/P conversion circuit 10b. When the synchronization is not established, a synchronization discrimination control circuit 11a gives a clock inhibit signal h1 to a clock inhibit circuit 9a. As a result, a bit phase between the signals g1 and b1 is changed by n-bits. When the bit phase is not yet synchronized at this point of time, the circuit 11a outputs a selection signal to the circuit 12 to change an output bit phase of the signal b1 by one bit phase. The bit synchronization is established between the signals g1 and b1 by repeating the operation above. |
