HIGH-DEFINITION TELEVISION RECEIVER

摘要

PURPOSE:To provide a high-definition TV receiver which can reduce the capacity of an image memory and also can reduce the scale of a signal processing circuit. CONSTITUTION:In an inter-frame interpolation circuit 112, the digital MUSE signals are coded by a coder 401 so that the coded signals whose bit numbers are reduced per pixel are written in the field memories 402a and 402b. The signal of the present field and the signal of the precedent field are acquired from the decoders 403a and 403b respectively and supplied to a multiplexer 420. The signals which are multiplexed in time division by the multiplexer 420 are processed by an LPF 421 of a single system and a sampling frequency converter 422 and separated into the signals corresponding to the present and precedent fields respectively by a demultiplexer 423. These separated signals are processed by an inter-field interpolation circuit 20 and outputted. Thus the memory capacity and the circuit scale can be reduced since the signals are processed in both coding and time division multiplexing states.