| 摘要 |
PURPOSE:To prevent an unstable state attended with frequent fluctuation in a period of a frame pulse for a secondary clock caused by a phase fluctuation in a primary clock by changing a load signal level to a counter section when a leading position of the primary frame pulse comes to a position at the outside of a permissible fluctuation range. CONSTITUTION:An FP permissible range detection section 7 detects an edge position of a primary frame pulse(FP1) being an input signal from a decoded output of a counter section 2. Then all the fluctuation range of the FP1 edge position with respect to a reference clock is selected to be a permissible range of a frame pulse(FP) synchronously with a secondary frame pulse(FP2). When the FP1 stays in the FP permissible range, it is regarded that the FP1 is synchronously with the FP2, a loading signal to the counter section 2 is inhibited to allow the counter section 2 to run itself. When the FP1 comes to a position at the outside of the frame pulse permissible range, a load signal level to the counter section 2 is changed depending on the fluctuated position to extend or reduce the period of the FP2. |
