| 摘要 |
<p>PURPOSE:To reduce the memory capacity of the entire multiplexer circuit. CONSTITUTION:With respect to a multiplexer circuit outputting input signals comprising n sets of input series with multiplexing for each information accommodation unit whose length is m, n-sets of data memories 131 to 134 storing the input signals of each input series are provided and k-th data memory (k is 1 to n) has a capacity of (1+k/n)Xm. Furthermore, the multiplexer is provided with n write address generating means 142 to 145 generating a write address signal for the capacity of corresponding data memory at all times, with n read address generating means 114 to 117 and 139 to 141 generating a read address signal by a capacity of the corresponding memory at a speed being a multiple of n of the write address signal and in which each generating period is a period decided to itself among n divisions of one period of the information accommodation unit equally divided and also with selection means 130, 140 selecting a signal read from each data memory synchronously with the read operation.</p> |
