| 摘要 |
PURPOSE:To reduce a synchronization clock time and to realize stable clock recovery. CONSTITUTION:A position detection circuit 13 generates position signals c1-c16 from an edge detection signal (b) and a flip-flop 14 segments the position signals c1-c16 at the leading of a recovered clock signal to provide an output of error signals d1-d16. A control circuit 15 generates a gate signal (f) and a UD discrimination signal (g) used to control a count of an up-down counter 19 and an up/down counting direction based on the error signals d1-d16. Then the up-down counter 19 counts the gate signal (f) and the UD discrimination signal (g) and provides an output of a 1-pulse addition signal (h) or a 1-pulse elimination signal (i) when the count reaches a setting count. A variable frequency divider circuit 110 conducts phase correction and frequency division and provides an output of a recovered clock signal (k). |
