| 摘要 |
<p>PURPOSE:To obtain a signal processor in which the phase of the operating clock such as A/D conversion clock is optimized. CONSTITUTION:An eye pattern obtained by applying reproduction data of a tape 1 from an integration system reproduction equalizer 4 to an equalizer of the PR (1, -1) system comprising a 1-bit delay circuit 5 and a subtractor 6 is converted into digital data by an A/D converter 7 and the data are decoded and reproduced by circuits after a Viterbi decoder 8. On the other hand, when a pattern detection circuit 13 detects a specific pattern of the digital data, the pattern is latched by a latch circuit 14. Since the output of the latch indicates the phase of the digital data, an oscillator 17 is controlled by a voltage resulting from D/A conversion of the data and its oscillating output is defined as an A/D conversion clock for the A/D converter 7, and also as an operating clock of other circuits. Thus, a PLL circuit optimizing the phase of the clock is formed and signal processing with less error is conducted.</p> |
