发明名称 PROCEDE ET DISPOSITIF DE SECURISATION DU DEROULEMENT DE SEQUENCES LINEAIRES D'ORDRES EXECUTES PAR UNPROCESSEUR
摘要 The error detection procedure associates each word (11,12,13) of the program sequence with a bit of the address word so that the order of the program words corresponds to a predefined order of bits in the address word. One bit (16) of each program word is not used in determining the instruction. The value of this unused bit is delivered to a logic function whose result is used to set the address word bit. When the program memory is read, the address bit is determined according to the order of the word read in the sequence. Its value is compared to the value obtained by applying the logic function to the unused bit of the instruction. An error signal is emitted if they differ. The preferred logic function is computation of the parity bit. <IMAGE>
申请公布号 FR2723222(A1) 申请公布日期 1996.02.02
申请号 FR19940009284 申请日期 1994.07.27
申请人 SEXTANT AVIONIQUE SA 发明人 PITOT CHRISTIAN;MARTINEZ MICHEL
分类号 G06F12/16;G06F11/10;G06F11/28;(IPC1-7):G06F11/00;G06F19/00 主分类号 G06F12/16
代理机构 代理人
主权项
地址