| 摘要 |
PURPOSE:To keep an optimal operational timing of an FET switch by oscillating a switching control signal at a specific frequency or below and controlling a variable delay time generating means to generate a delay time for minimizing the peak value of surge current every specific period of the oscillation frequency. CONSTITUTION:The delay time is controlled variably by delay time control means for circuit 3-5, 28 which receives a switching control signal being fed to an FET switch 7 for switching an input current F from a DC power supply 1. The delay time is imparted repetitively, by circuits 43-48, 50, 51, 53, with a subtle incremental/decremental variation every one half period of the oscillation frequency at a frequency of one tenth of that of the switching control signal or below. The delay time is controlled by circuits 26, 33, 37, 40-43, 52 such that the peak value of surge current is minimized by voltage circuits 20-25 in proportion to the peak value of input surge current F thus eliminating the need of high speed high response component. |
