发明名称 PROGRAMMABLE LOGIC ARRAY
摘要 PURPOSE:To reduce the power consumption and to attain high processing speed by providing a discharge circuit discharging each block to each block. CONSTITUTION:MOS transistors (TRs) of each of MOS TR arrays 1-0 to 1-r are connected in series with lines L0-Ln. A precharge level is applied to one and other terminals of the lines L0-Ln and nodes 3-0 to3-(r-1) of the lines L0-Ln among the MOS TR arrays 1-0 to 1-r from precharge circuits 2-0 to 2-4 and a precharge/discharge circuit 4 in the case of precharge. The precharge/ discharge circuit 4 applies a discharge potential to the other ends of the lines L0-Ln in the discharging state.
申请公布号 JPH0832439(A) 申请公布日期 1996.02.02
申请号 JP19940164063 申请日期 1994.07.15
申请人 TOSHIBA CORP 发明人 NAKADA SHIGEJI;ISHII YASUHIRO
分类号 G06F7/00;G06F7/57;G06F7/575;H03K19/177 主分类号 G06F7/00
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