发明名称 VITERBI ACS UNIT WITH RENORMALIZATION
摘要 In a Viterbi decoder including an add-compare-select (ACS) processor (ACS0, ACS1,... ACS63), speed is enhanced without loss of performance by maintaining a dynamic cumulative metric range for computed metrics to obtain two computed metrics, and the smaller of the two computed metrics is stored along with previously computed state metrics. In the renormalization circuit (RENORM), the stored state metrics are compared with a selected scale factor, for example one-half maximum scale factor, and all current state metrics are rescaled when the minimum stored metric value exceeds the selected scale factor.
申请公布号 WO9602973(A1) 申请公布日期 1996.02.01
申请号 WO1994US07957 申请日期 1994.07.15
申请人 STANFORD TELECOMMUNICATIONS, INC. 发明人 GRAHAM, HATCH;NGUYEN, CHRISTINE
分类号 H03M13/41;(IPC1-7):H03D1/00;H03M13/00;H04L5/12;H04L23/02;H04L27/06;G06F11/10 主分类号 H03M13/41
代理机构 代理人
主权项
地址