发明名称 VITERBI ACS UNIT WITH RENORMALIZATION
摘要 <p>In a Viterbi decoder including an add-compare-select (ACS) processor (ACS0, ACS1,... ACS63), speed is enhanced without loss of performance by maintaining a dynamic cumulative metric range for computed metrics to obtain two computed metrics, and the smaller of the two computed metrics is stored along with previously computed state metrics. In the renormalization circuit (RENORM), the stored state metrics are compared with a selected scale factor, for example one-half maximum scale factor, and all current state metrics are rescaled when the minimum stored metric value exceeds the selected scale factor.</p>
申请公布号 WO1996002973(A1) 申请公布日期 1996.02.01
申请号 US1994007957 申请日期 1994.07.15
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