| 摘要 |
PURPOSE:To reduce the scale of circuitry by dividing a memory and allocating the memory to a plurality of receiving channels so that a memory space multiplexes the I/O collectively for the channel group. CONSTITUTION:Upon receiving address signals ADR1, ADR2, single ports RAMa 141, 142,...,14n are operated as a single RAM. Address decoders 101, 102 decode the address signals ADR1, ADR2 so that any memory space of the single port RAM 141, 142,...,14n corresponds with a read or write address. The address decoder 101, 102 delivers an address signal ADR having word length shorter than the address signal ADR1, ADR2 to any one of the single ports RAMa 141, 142,...,14n. The address signals ADR1, ADR2 are inputted such that the read and write addresses do not correspond with a same single port RAM. |
