发明名称 |
Improved neural semiconductor chip architectures and neural networks incorporated therein |
摘要 |
There is disclosed the architecture of a neural semiconductor chip (10) first including a neuron unit (11(#)) comprised of a plurality of neuron circuits (11-1, ...) fed by different buses transporting data such as the input vector data, set-up parameters, ... and control signals. Each neuron circuit (11) includes means for generating local result (F, ... ) signals of the "fire" type and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip. An additional OR function is then performed between all corresponding first global result and output signals to generate second global result (R**) and output (OUT**) signals, preferably by dotting on an off-chip common communication bus (COM**-BUS) in the driver block (19). This latter bus is shared by all the neural chips that are connected thereon to incorporate a neural network of the desired size. In the chip, a multiplexer (21) may select either the first or second global output signal to be reinjected in all neuron circuits of the neural network as a feed-back signal depending on the chip operates in a single or multi-chip environment via a feed-back bus (OR-BUS). The feedback signal results of a collective processing of all the local signal. <MATH> |
申请公布号 |
EP0694854(A1) |
申请公布日期 |
1996.01.31 |
申请号 |
EP19940480070 |
申请日期 |
1994.07.28 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;PAILLET, GUY |
发明人 |
STEIMLE, ANDRE;PAILLET, GUY;TANNHOF, PASCAL |
分类号 |
G06F15/18;G06N3/00;G06N3/04;G06N3/06;G06N3/063 |
主分类号 |
G06F15/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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