| 摘要 |
A digital phase-locked loop circuit includes circuitry for generating substantially periodic recovered clock signals each one corresponding to a discrete amount of delay from a local clock signal. Incremental delay is added or subtracted at each clock generation cycle until the data input signal and the last-generated recovered clock signal are substantially phase-aligned. The circuit includes delay measurement circuitry for dynamically measuring the smallest quantity of delay units required to provide at least a 360 degree phase shift of the local clock signal. The circuitry for generating the recovered clock signals is then constrained to generate clock signals having a maximum delay corresponding to the last-measured quantity of delay.
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