Noise elimination circuit for clock pulse sequence

摘要

The circuit has a holding stage (G1,G2) with a bistable switching characteristic receiving the clock pulse sequence for providing a potential jump at the beginning and end of each clock pulse of fixed amplitude, independent of the actual pulse amplitude. The potential value at the input of the circuit is held for a time interval sufficient for removal of the noise at the beginning and end of each pulse, controlled by the circuit output which is fed to a delay stage (V) which prevents further potential jumps until the end of a defined delay time.