Verfahren zum Testen von hierarchisch organisierten integrierten Schaltungen und integrierte Schaltungen, geeignet für einen solchen Test.

摘要

A method for testing a hierarchically organized integrated circuit means first attacks each assembly in sequence thereof, and in each assembly executing an assembly test cycle. Each assembly test cycle within the assembly in question attacks each macro thereof in sequence and conditionally executes therein a test run under selective control of a macro test mode (MTM) signal. The number of hierarchy levels may be three or more. The method may be applicable to separate integrated circuits or to a wired board with a plurality of circuits.