Apparatus and method for generating negative bias for isolated mosfet gate-drive circuits

摘要

An isolated MOSFET gate drive includes circuitry to provide a negative gate bias during the off time of the MOSFET (Q1) to enhance its immunity to inadvertent turn-on. The bias is generated by a self contained two terminal passive network (C1,CR4) which may be "floated" at any potential with respect to ground. This bias is automatically generated through the action of the network to the gate drive waveform, eliminating the need for an external bias supply to provide this voltage. The bias supply is located locally, thus eliminating the need for long interconnects which may interfere with circuit operation. The bias network in one implementation is a combination of a capacitor (C1) and non-linear semiconductor device (CR4) with a fixed voltage breakdown characteristic. This two-component implementation maintains the capability of producing systems with high packaging densities.